Large-scale integration of components in data packet switching technology, such as Ethernet switching technology, has led to complete data packet switches being constructed or produced on a single chip or within a single unit. These single-unit data packet switches typically include a switching matrix, input/output port buffers, common shared memory pools, switching/routing tables and all other functions required to perform data packet switching and are commonly used for routing packets in a network or system backplane based on various criteria as appropriate to particular circumstances.
This large-scale integration in data packet switching technology has led to decreased cost for the production of data packet switches and has decreased the number of external components required to achieve the same switching capability over previously available data packet switches. However, this integration has the disadvantage of decreased flexibility in a system using a single-unit data packet switch, as a whole. This decrease in flexibility is primarily due to various design tradeoffs that are made in order to increase the efficiency of single-unit data packet switch construction. For example, such single-unit data packet switches are often optimized for typical network or backplane deployments with the expectation of randomized data flows across all input and output ports of the switch. In certain circumstances, such as network monitoring, port aggregation, and/or link load balancing, egress ports of a single-unit data packet switch may be easily oversubscribed on a temporary basis, for example, when highly intensive data streams, such as data streams including video information, are transmitted. This over-subscription typically leads to packet loss, as the buffer space of the typical single-unit data packet switch chip is fully utilized within a few hundred or a few thousand data packets. The capability of the buffer available inside a typical single-unit data packet switch is thus inadequate as the line rate, or the traffic flow rate of data packets across or entering the switch, increases. For example, at a line rate of ten gigabits per second or more, such small buffer sizes are of little value, especially when bursts of hundreds of thousands of packets may need to be momentarily deferred or equalized across slower speed exit ports of the integrated data packet switch.
Providing appropriately large buffer sizing in commodity or commercially available single-unit data packet switches would drive the cost of these devices significantly higher and have limited benefit to all but a few specific uses and therefore, would benefit a relatively small percentage of users. Thus, there is little economic incentive to produce single-unit data packet switches with internal memories large enough to buffer large bursts of thousands of data packets for the relatively small proportion of data packet switch applications that require such large internal buffering capability.